The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of patterning metallization lines in metallization layers of integrated circuits.
Metallization layers in integrated circuits allow for electrical connection between layers of integrated circuits and external devices. As circuit sizes have continued to shrink, new methods for patterning and forming metallization lines, such as self-aligned multiple patterning techniques, continue to be developed to overcome limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metallization patterns.